1. Field of the Invention
The present invention relates to planar lightguide circuits (PLCs) and, in particular, to PLCs incorporating more than one optical device thereon.
2. Description of the Related Art
In the marketplace for optical components for telecommunications systems, there is an ever-increasing desire for more compact components which include more than one device function. One known way of attempting to achieve this is to integrate more than one optical device in a planar integrated circuit (PLC) chip. Each device comprises waveguides appropriately arranged on the chip to provide desired device functions. For example, an arrayed waveguide grating (AWG) and a power tap (sometimes also referred to as a “tap coupler”) can be integrated on a single PLC chip.
In designing any optical device for fabrication on a PLC, the design and fabrication of the optical waveguides is very important. The dimensions of the waveguides, and the separation of one waveguide from another, influence the stress on the waveguides, and hence the birefringence exhibited by the waveguide. The waveguide birefringence may give rise to undesirable polarization dependence properties such as polarization dependent loss (PDL) and polarization dependent wavelength (known commonly as “splitting”) of the optical device. For most component manufacturers and their customers it is important for the waveguide birefringence (B) through the device to be as low as possible, ideally zero, where B is commonly defined as the difference between the effective refractive indices experienced by TM and TE polarized light:B=nTM−nTE 
Although the mechanism by which the birefringence arises has not been proven, it is thought to result from the differences in thermal expansion properties between layers in the device structures, which causes stresses to build up when the device is cooled after sintering or annealing. International Patent Application, WO 02/14916, the entire contents of which are hereby incorporated herein by reference, describes a manufacturing technique, which has been invented for controlling and minimizing birefringence in waveguides. In this technique, which is herein referred to as the “over-etch” technique, during the step of etching the waveguide core, the etching is continued beyond the desired core depth, so that the final waveguide core sits on a mesa structure. The technique is here illustrated in FIGS. 1(a) to 1(f). These figures are highly schematic and are, in any case, not to scale. FIG. 1(a) illustrates a silicon substrate 10 on which a thick (e.g. approx 16 μm) thermal oxide undercladding layer 20 is then grown (see FIG. 1(b)). In FIG. 1(c) a layer of waveguide core glass 30 is deposited, for example by Flame Hydrolysis Deposition (FHD). This deposited layer may then be annealed to consolidate it. A mask 40 is then applied to mask the path of a desired waveguide core. The mask can be a metal mask formed by photographically spinning and exposing a resist layer, followed by development and coating with a metal layer by evaporation. The resist and its cover of metal can be lifted off with acetone to leave the metal mask 40. Alternatively, the mask may be made using other known mask materials, such as photoresist or silicon. In FIG. 1(d) an etching step is carried out using conventional wet or dry etching techniques. The etching etches away the parts of the core waveguide layer 30 not covered by the mask 40 (i.e. the regions forming the complement of the desired waveguide path are removed from the layer 30) until the thermal oxide undercladding layer 20 is reached. This leaves the waveguide core 50, which in this example has a substantially square cross-section. In a conventional fabrication process the next step would be to remove the mask 40 and apply an overcladding layer 70 to the structure of FIG. 1(d), but in the inventive process of WO 02/14916 the etching process is continued, still using the mask 40 to define the regions to be etched, so as to etch away part of the undercladding layer 20 in the regions not protected by the mask 40. This “over-etching” process leaves an undercladding layer 20 which is thinner across most of the device but which forms a mesa formation 60 substantially covered by the core 50, as shown in FIG. 1(e). The height d of the mesa formation is herein referred to as the “over-etch depth”. The mask 40 is removed and an overcladding layer 70 is then applied to the structure, covering the waveguide core 50 and the oxide undercladding 20, as shown in FIG. 1(f). The over-etch depth is chosen by the PLC designer so as to achieve a desired birefringence in the waveguide, normally to try and achieve the minimum possible birefringence, preferably substantially zero birefringence. Typically, for an AWG an over-etch depth of between 2 and 4 μm is used for the array waveguides. One problem which the designer faces when designing an integrated optical component incorporating multiple device functions is that for different devices integrated on the PLC chip, the aforementioned technique results in the same over-etch depth being applied to all devices present on the PLC chip. In fact, the ideal over-etch for one device may not be the same as the ideal over-etch for another device to be fabricated on the same chip. i.e. the over-etch depth necessary to achieve minimum birefringence in the waveguides of one device may be too shallow, or too deep, an over-etch to achieve minimum birefringence in the waveguides of another device on the same chip. This is particularly the case where there are to be different sets of waveguides with different spatial arrangements on the same PLC chip. For example, where one device is an AWG, there will be a number of very closely spaced channel waveguides forming the array of the AWG and where another device is a tap coupler there may be only two waveguides arranged in a Mach-Zender relationship with a spacing between the two waveguides different to the average array waveguide spacing of the AWG.
It is an aim of the present invention to avoid or minimize one or more of the foregoing disadvantages.
For the avoidance of doubt, the term “different devices” will herein be used to mean not only devices having different functions (e.g. an AWG and a tap coupler), but also to mean any two devices having the same function but designed to be of different size or dimensions and/or to perform differently (e.g. two AWGs having a different number and spacing of arrayed waveguides).